The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a fin field effect transistor (finFET) containing an III-V compound semiconductor fin and an undercut extension region located beneath a dielectric spacer that is present on each vertical sidewall of a functional gate structure and a method of forming the same.
Throughout the evolution and advancement of semiconductor devices, reducing the size and power consumption of the devices, while maintaining or improving a high processing capacity have long been design goals. Planar field-effect transistor (FET) devices, which have been widely used in integrated circuits for the past several decades, have been found to be increasingly inefficient on the nanometer scale. Reducing the size of the channel between the terminals of planar transistors to this scale leads to an inefficient leakage of current in the off-state of the transistor, resulting in an increase in power consumption in its idle state.
Multi-gate field-effect transistors (MuGFET) have been developed to address this problem, as such transistors incorporate several gates that surround the channel between a source and drain terminal of the transistor on a plurality of surfaces, thereby enabling the suppression of leakage current in the off-state. There are several different types of multi-gate devices. FinFET and Trigate devices are two examples. FinFET devices include a thin fin, which can be made of silicon, that provides the channel between a source and a drain. The fin can be overlaid with one or more pairs of gates, where the gates in a pair are on opposing sides of the fin.